电子科技大学“数字逻辑设计及应用”数字逻辑2-2.pptVIP

Steady state : voltage and current Chapter 2 Digital circuit design for logic unit Steady model of CMOS When Vx is increased, Rn will be increased and Rp decreased ! The steady state model of CMOS Figure 3-8 3-9 The output voltage is changed When input voltage changed. The steady state model of CMOS The input between VIL and VIH : Amplified area ! Logic level and noise margin Logic level and noise margin The input limit : avoid the noise be amplified! Output current: driving ability Minimal area means minimal driving ability Design for minimal device Specifications for two kind load: CM