电子科技大学“数字逻辑设计及应用”数字逻辑2-3.pptVIP

Time delay and power consumption Interface design for IC package Chapter 2 Digital circuit design for logic unit Dynamic model of CMOS Any device has its input and output capacitors Dynamic model of CMOS Dynamic behavior When state changed, capacitors must be charged or uncharged through a resistor ! Time delay rely on capacitance for charge or uncharge ,and capacitance of a unit decided by its logic area. Time delay in logic device Dynamic power consumption Power consumption is mainly happened when the state is changed! Parallel design for logic unit Parallel design may be get less t