电子科技大学“数字逻辑设计及应用”数字逻辑6-3.pptVIP

Synchronize design for asynchronous input Chapter 6 Sequential control design principles Come from other system： input device、internet、other computer Maybe changed at any time Asynchronous signal Signal maybe lost Signal maybe changed in sampling window Asynchronous signal Change the series signal to parallel signal : less change Set a buffer area : more stable Asynchronous signal Synchronizer design Synchronizer design For low frequency signal : Synchronizer design For high frequency signal : OK signal is asynchronies signal Enable signal maybe metastable Synchronizer design Synchroniz