电子科技大学“数字逻辑设计及应用”数字逻辑7-2.pptVIP

* * FSM design: counter Chapter 7 Finite state machine design State-machine design Design of Counters A Moore machine with single state circle. Q: states output; R: last state . A mode 5 counter design state diagram State assignment binary code Gray code S0 0 0 0 0 0 0 S1 0 0 1 0 0 1 S2 0 1 0 0 1 1 S3 0 1 1 0 1 0 S4 1 0 0 1 1 0 Encode for states Q2 Q1 Q0 Q2 Q1 Q0 Transition/output table binary code Gray code Minimal risk or minimal cost design Minimal risk Minimal cost