jtag(jointtestactiongroup)是1985年制定的检测pcb和.docVIP

JTAG (Joint Test Action Group)是1985年制定的检测PCB和IC芯片的一个标准，1990年被修改后成为IEEE的一个标准，即IEEE1149.1-1990。通过这个标准，可对具有JTAG接口的芯片的硬件电路进行边界扫描和故障检测。具有JTAG接口的芯片,相关JTAG引脚的定义为:TCK为测试时钟输入；TDI为测试数据输入，数据通过TDI引脚输入JTAG接口；TDO为测试数据输出，数据通过TDO引脚从JTAG接口输出；TMS为测试模式选择，TMS用来设置JTAG接口处于某种特定的测试模式；TRST为测试复位，输入引脚，低电平有效。?什么叫JTAG？JTAG，它是Joint Test Action Group缩写，是IEEE的标准规范，ARM7TDMI内部提供了3个JTAG型的扫描链，可以进行调试和配置嵌入式的ICE-RT逻辑。JTAG仿真器也称为JTAG调试器，是通过ARM芯片上的JTAG边界扫描口进行调试的设备。JTAG仿真器比较便宜，连接比较方便。它可以通过现有的JTAG边界扫描与ARM CPU核进行通信，属于完全非插入式调试。它无需目标存储器，不占用目标系统的任何端口。JTAG InterfaceJTAG Bus DescriptionIEEE Std 1149.1-1990 JTAG (Joint Test Action Group); Test Access Port and Boundary-Scan Architecture. This is a serial bus with four signals: Test Clock (TCK), Test Mode Select (TMS), Test Data Input (TDI), and Test Data Output (TDO). The bus is used as a test bus for the Boundary-Scan of ICs, as in Design-For-Testability (DFT). To use JTAG, during the design, you most select JTAG compatible devices. ICs supporting JTAG will have the four additional pins listed above. Devices reside on the bus in a daisy chain, with TDO of one device feeding TDI of the next device. In addition to having the pins listed above each device most have a Boundary-Scan Register. The Boundary-Scan Register may be used to test the interconnection between ICs [Chip-to-Chip] or test with in the IC. Boundary-scan tests can be used to check continuity between devices. Continuity checks on PWB nets may be performed by sending out a know pattern and receiving that same pattern at the input to another IC(s). Not receiving the test signal or pattern would indicate a broken PWB trace, a failed IC, or cold solder joint.TCK: [Test Clock] has noting to do with the board or system clock. The Test Clock is used to load the test mode data from the TMS pin, and the test data on the TDI pin [on the rising edge]. On the falling edge test clock outputs the test data on the TDO pin.TMS: [Test Mode Select Input] controls the operation of the test logic, by receivin