012-msCAN.ppt.pptVIP

CAN SPECIFICATION CAN PROPERTIES msCAN - Layered Architecture msCAN12 Buffer Scheme Simple user interface to CPU Message filtering and buffering Protocol handling Physical layer interface Extended Format Frames Standard Format Frames Frame Types DATA FRAME ARBITRATION FIELD STANDARD Vs. EXTENDED I.D. FORMAT CONTROL FIELD CRC ACKNOWLEDGEMENT FIELDS REMOTE FRAME ERROR FRAME OVERLOAD FRAME INTERFRAME SPACE MESSAGE ARBITRATION ERROR DETECTION FAULT CONFINEMENT ERROR SIGNALING Bit Timing SYNC_SEG : The bit edge is expected to lie within this segment ; always 1 time quantum (CAN clock period) long. PROP_SEG : Allowance for physical delays. Programmable from 1 to 8 TQ long. PROP_SEG = 2 x ? (bus propagation delay + input comparator delay + output driver delay) PHASE_SEG (1, 2) : Defines position of the Sample Point. May be adjusted to compensate for edge phase errors PHASE_SEG1: Programmable from 1 to 8 time quanta long. PHASE_SEG2: Is the greater of PHASE_SEG1 and the INFORMATION PROCESSING TIME. SAMPLE POINT : Bus value is taken as the value of the bit INFORMATION PROCESSING TIME: Less than or equal to 2 time quanta. BIT TIME : Bit Time = SYNC_SEG + PROP_SEG + PHASE_SEG1 + PHASE_SEG2 msCAN Bus Timing (1 of 2) msCAN Bit Timing (2 of 2) SAMP: 1 or 3 samples per bit TSEG1 is determined by TSEG13...TSEG10 TSEG2 is determined by TSEG22...TSEG20 SYNCHRONIZATION Resynchronization (2) CANPHYSICAL LAYER REQUIREMENTS msCAN MB Identifier Registers msCAN MB Data Registers msCAN Acceptance Registers (2x32 Bit Filter) msCAN Message Acceptance Mask msCAN Message Acceptance Registers (4x16 bit filter) msCAN Acceptance Registers (8x8 Bit Filter) msCAN Acceptance Filter Each Acceptance Register has a corresponding Acceptance Mask Register. Any bit set in an Acceptance Mask Register means that bit in the Acceptance Register is masked, ie. not compared with the Message Identifier to determine acceptance. Only bits in the Acceptance Register which are not