数电课件ch_07_st1_.ppt

Selected Key Terms Propagation delay time Set-up time Hold time Timer The interval of time required after an input signal has been applied for the resulting output signal to change. The time interval required for the input levels to be on a digital circuit. The time interval required for the input levels to remain steady to a flip-flop after the triggering edge in order to reliably activate the device. A circuit that can be used as a one-shot or as an oscillator. 1. The output of a D latch will not change if a. the output is LOW b. Enable is not active c. D is LOW d. all of the above ? 2008 Pearson Education 2. The D flip-flop shown will a. set on the next clock pulse b. reset on the next clock pulse c. latch on the next clock pulse d. toggle on the next clock pulse ? 2008 Pearson Education CLK D CLK Q Q 3. For the J-K flip-flop shown, the number of inputs that are asynchronous is a. 1 b. 2 c. 3 d. 4 ? 2008 Pearson Education CLK K J Q Q PRE CLR 4. Assume the output is initially HIGH on a leading edge triggered J-K flip flop. For the inputs shown, the output will go from HIGH to LOW on which clock pulse? a. 1 b. 2 c. 3 d. 4 ? 2008 Pearson Education CLK K J 1 2 3 4 5. The time interval illustrated is called a. tPHL b. tPLH c. set-up time d. hold time ? 2008 Pearson Education 50% point on triggering edge 50% point on LOW-to-HIGH transition of Q CLK Q ? ? 2008 Pearson Education CLK D ? 6. The time interval illustrated is called a. tPHL b. tPLH c. set-up time d. hold time 7. The application illustrated is a a. astable multivibrator b. data storage device c. frequency multiplier d. frequency divider ? 2008 Pearson Education HIGH HIGH CLK K J QA CLK K J fin QB fout ? 2008 Pearson Education 8. The application illustrated is a a. astable multivibrator b. data storage device c. frequency multiplier d. frequency divider Parallel data input lines Clock Clear Output li