ESD class 4 ESD protection scheme non_snapback based and ESD current path.pptVIP

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2017-03-26 发布于江苏
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ESD class 4 ESD protection scheme non_snapback based and ESD current path.ppt

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ESD class 4 ESD protection scheme non_snapback based and ESD current path

Class 4(1) ESD protection scheme – non-snapback based(2)ESD current path ESD protection – non-snapback based Diode under forward bias Parasitic diode Intended diode Large enough active power clamp Gate-couple NMOS Gate-driven NMOS Diode under forward bias Low turn-on voltage Large current capability Diode classification P+/N-well diode can be cascaded as diode string, but need to note the Darlington amplification effect N+/P-well (P-sub) diode N-well/P-well (P-sub) diode Parasitic PNP in P+/N-well diode Area index or perimeter index? (LV p-diode forward) Area index or perimeter index? (LV p-diode reverse) TLP I-V for LV diode (reverse) Active power clamp The advantages of active power clamp Uniform conduction of multi-finger ESD device Could be SPICE simulated Predictable No stringent ESD-related rules The disadvantages of active power clamp Large device size Large RC time constant and large layout size Key parameters of active power ESD clamp Clamp voltage Layout area Leakage current drawn during power-up Quiescent VDD to GND leakage current Immunity to mis-triggering during normal operation conditions Trigger time of power clamp for CDM stress Popular active power clamp Effect of device width Effect of time constant Mis-triggering under fast power-on Dual-diode (double-diode) protection scheme Dual-diode (double-diode) protection scheme -- Evaluation example Effect of VSS routing for I/O circuit Possible current paths with separate power supply— Stress Vcc1 vs. Vss2 or Vcc2 Clamping diode for inter-core interface issue The effect of interface clamping diode * Confidential Meng Liu Diode linear region Diode saturation region I V P+ N+ N-well N+ P-sub Depend on the well process (diffused or retrograde), the current gain of parasitic PNP BJT is different. For diffused well, the current gain is high ( 10), and the BJT effect is significant. For retrograde well, the current gain is low ( 10), and the BJT effect is not significant. Optimum diode layout As large