ARM11_MPCore.pptVIP

ARM 11 MPCore Presented by, Naveen Kalla Vivek Tamma Topics What is ARM ? ARM11 MPCore ARM v6K architecture Memory Management Units (MMUs) Cache Memory Interrupts What is ARM? Advanced RISC Machine 32-bit processor with 16-bit 8-bit modes Low Power Consumption Low latency input/output (interrupt) handling High Code Density – Thumb mode Load Store Architecture non-intrusive way of extending the instruction set using coprocessors“ ARM11 MPCore ARM11 MPCore (Contd.) Up to 4 CPUs implementing ARM v6K Snoop Control Unit – Cache Coherency Distributed Interrupt Controller Private Timer and Private Watchdog for each CPU AXI high speed Advanced Microprocessor Bus Architecture (AMBA) level two interfaces MP11 CPU Pipeline Stages ARMv6 features 7 modes of operation (usr, fiq, irq, svc, abt, sys, und) Register Banks and Link Register Branch prediction with 3-entry return stack Conditional Code Execution Branch Prediction Dynamic branch prediction 128-entry Branch target Address Cache (BTAC) 2-bit prediction history bits Static branch prediction Cache Instruction and data caches, including a non-blocking data cache with Hit-Under-Miss (HUM) Data cache is physically indexed, physically tagged, write back, write allocate only Instruction cache is virtually indexed, physically tagged 32-bit interface to the instruction cache and 64-bit interface to the data cache Hardware support for data cache coherency The instruction and data cache can be independently configured during synthesis to sizes between 16KB and 64KB. Cache (continued…) Both caches are 4-way set-associative. Cache replacement policy is round-robin. The cache line length is eight words. Both data cache read misses and write misses are non-blocking. Up to three outstanding data cache read misses and up to four outstanding data cache write misses are supported. Support is provided for streaming of sequential data from LDM and LDRD operations, and for sequential instruction fetches. On a cache-miss, critical word fi