中科院数字集成系统设计作业.docVIP

声明 鉴于本人水平有限，所发作业答案仅供参考。希望同学们能继续完善！ Assignment 2: Access the relevant reference books or technical data books and give accurate definitions for the following timing parameters: (1) propagation time tPD, 传输延迟从输入脉冲到引起输出电平跳变之间的时间间隔。transition time tTD, The transition time is the time a dynamical system needs to switch between two different stable states, when responding to a stable input signal. In a logic circuit (a discrete-time dynamical system whose state is representable as a boolean-valued vector function of time) undergoing a change of state, it identifies the rise time or the fall time of the output voltage. It is therefore correct to speak of two types of transition times. (3) setup time tSU, Setup time is the amount of time before the clock edge that the input signal needs to be stable to guarantee it is accepted properly on the clock edge.即建立时间是指触发器的时钟信号上升沿到来以前，数据稳定不变的时间。输入信号应提前时钟上升沿（如上升沿有效）到达时间Hold time is the amount of time after the clock edge that same input signal has to be held before changing it to make sure it is sensed properly at the clock edge.即保持时间是指触发器的时钟信号上升沿到来以后，数据稳定不变的时间。The clock to output time is the worst case time it takes for a signal to propagate out after the clock edge.即输出时钟时间，为了使信号正常输出，时钟信号在时钟沿到来之后仍需要保持的时间。 Compare the main features of 74-393 and 74-163 counters and construct an N-bit synchronous counter using 74-163(s). 74-393 counters ? Two 4-bit binary counters with individual clocks ? Divide-by any binary module up to 28 in one package ? Two master resets to clear each 4-bit counter individually ? Output capability: standard ? ICC category: MSI 74-163 counters ? Synchronous counting and loading ? Two count enable inputs for n-bit cascading ? Positive-edge triggered clock ? Synchronous reset ? Output capability: standard ? ICC category: MSI 综上，74-393 counters是异步的，74-163 counters具有同步计数、置数、清0功能；是上升沿触发。 1至16进制，Q1Q2Q3Q4端由与非门直接连回RESET端。16进制以上需要级联两个至多个74-163 counters。级联时将进位端接到CEP和CET端，共用时钟信号。（图略） Macrocells (MCs) are key c