Lecture5简单数字电路的设计—组合电路—v2-0.pptVIP

* Verilog HDL语言 华中科技大学计算机科学与技术学院 主讲：胡迪青 Email: hudq024@mail.hust.edu.cn QQ: 121374333 Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. 简单数字电路设计 Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. 设计验证与仿真 Verilog HDL不仅提供描述设计的能力，而且提供对激励、控制、存储响应和设计验证的建模能力。 激励和控制可用初始化语句产生。验证运行过程中的响应可以作为“变化时保存”或作为选通的数据存储。 最后，设计验证可以通过在初始化语句中写入相应的语句自动与期望的响应值比较完成。 要测试一个设计块是否正确，就要用Verilog再写一个测试模块。这个测试模块应包括以下三个方面的内容： 测试模块中要调用到设计块，只有这样才能对它进行测试； 测试模块中应包含测试的激励信号源； 测试模块能够实施对输出信号的检测，并报告检测结果。 Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. * Simulating/Validating HDL The sad truth… 10% design, 90% validation If you do it right you will spend 9X more time testing/validating a design than designing it. Design Under Test (verilog) Stimulus Generation (verilog) Output Monitoring Self Checking (verilog) file file Verilog test bench shell Testbenchs are written in verilog as well. Testbench verilog is not describing hardware and can be thought of as more of a program. Evaluation only. Created with Aspose.Slides for .NET 3.5 Client Profile 5.2.0.0. Copyright 2004-2011 Aspose Pty Ltd. Testbench Example (contrived but valid) module test_and; integer file, i, code; reg a, b, expect, clock; wire out; parameter cycle = 20; and #4 a0(out, a, b); // Circuit under test initial begin : file_block clock = 0; file = $fopen(compare.txt, “r” ); for (i = 0; i 4; i=i+1) begin @(posedge clock) // Read stimulus on rising clock code = $fscanf(file, %b %b %b\n, a, b, expect); #(cycle - 1) // Compare just before end of cycle if (expect !== out) $strobe(%d %b %b %b %b, $time, a, b, expect, out); end // for $fclose(file); $stop; end // initial always #(cycle /2) clock = ~clock; // Clock generator endmodule Evaluation only. Created with Asp