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END THANK YOU！ * Chapter 8 李莉.信息机电学院. SHNU Linearcodes: 1 infor. bit ?1 codeword; (n,k)or [n,k,d]，k-bit infor. ? one n-bit codeword Convolution code:. 1 infor. bit ? m codewords; (n,k,m) k-bit infor.+m previous infor.bits ? 1 n-bit codeword Representation to convolution code: Algebraically, discrete convolution, generator matrices, polynomials; 解析法：离散卷积法、生成矩阵法、码多项式法； Graphically, tree, trellis, state diagrams. 图形法：树图法、格图法、状态图法. SHNU.信息机电学院 8.1 Convolution (卷积) The discrete convolution. 1)Linear feed-forward shift register the links: g0, g1, g2, g3, g4 = 0, the link is absent or 1, the link is present. Input sequence: u=( u0 u1, u2,u3,…) (输入码序列). output sequence: v=( v0 v1, v2,v3,…) (输出码序列). Assuming the initial states of the shift registers =0, output: 1st tick: v0=u0g0. 2nd tick: v1=u1g0+u0g1. 3rd, v2=u2g0+u1g1+u0g2. 4th , v3=u3g0+u2g1+u1g2+u0g3. (8.1) 5th , v4=u4g0+u3g1+u2g2+u1g3+u0g4. 6th , v5=u5g0+u4g1+u3g2+u2g3+u1g4. u v g4 g3 g2 g1 g0 ? A register with m stages each input ~ m+1 outputs. SHNU.信息机电学院 2) Outputs for a finite input sequence The last input should appear at the output, an addition m zero inputs are required. The input: u=(u0 u1 u2 … u7,0000), the last outputs: v7= u7g0+u6g1+u5g2+u4g3+u3g4. m=4 v8= u8g0+u7g1+u6g2+u5g3+u4g4. v9= u9g0+u8g1+u7g2+u6g3+u5g4. v10= u10g0+u9g1+u8g2+u7g3+u6g4. v11= u11g0+u10g1+u9g2+u8g3+u7g4. Setting u8=u9=u10=u11=0, All the 7 inputs appear at the output, the output sequence is completed. Any further zero inputs ? a zero output. The additional m 0 bits ? returns reg. to zero state. The m 0 should not be confused with the information bits. v8=u7g1+u6g2+u5g3+u4g4. v9= u7g2+u6g3+u5g4. v10= u7g3+u6g4. v11= u7g4. SHNU.信息机电学院 3)