Flash EEPROM parallel interface.pptVIP

Flash / EEPROM parallel interface 12/13/04 Jim Brandt, Team Leader Jeff Nault Project Objectives Project Objectives 100 MHz system clock interface 45 ns (Flash Read Time) interface 0 latency system interface Develop on and off chip testing methodologies to enable accurate testing of chip post- fabrication Keep design small and minimize power consumption Project Definition Project Definition EEPROM template memory interface for fingerprint recognition system: Will allow 0 latency for system memory by buffering data transfers between each. 16 bit parallel input from EEPROM and 2 b