段LED数码管显示译码器设计.docVIP

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity seven_seg is port ( clk,en : in std_logic; lock : in std_logic_vector(1 downto 0); din : in std_logic_vector(3 downto 0); dig : out std_logic_vector(2 downto 0); seg : out std_logic_vector(7 downto 0) ); end seven_seg; architecture rt1 of seven_seg is signal scan:std_logic_vector(2 downto 0); signal data_r:std_logic_vector(3 downto 0); signal seg_r:std_logic_vector(7 downto 0); signal d_r:std_logic_vector(15 downto 0); begin dig = scan; seg = seg_r; a:PROCESS(clk) BEGIN IF (clkeven