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Design and Analysis of On-Chip ESD Protection Circuit with Very Low Input.pdf

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Design and Analysis of On-Chip ESD Protection Circuit with Very Low Input

Analog Integrated Circuits and Signal Processing, 32, 257–278, 2002 ?C 2002 Kluwer Academic Publishers. Manufactured in The Netherlands. Design and Analysis of On-Chip ESD Protection Circuit with Very Low Input Capacitance for High-Precision Analog Applications MING-DOU KER, TUNG-YANG CHEN AND CHUNG-YU WU Integrated Circuits Systems Laboratory, Institute of Electronics, National Chiao-Tung University, 1001 Ta-Hsueh Road, Hsinchu, Taiwan 300, R.O.C. Tel.: (886) 3-5712121 ext. 54173, Fax: (886) 3-5715412 E-mail: mdker@ieee.org Received December 11, 1999; Revised August 31, 2000 Abstract. An ESD protection design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-rails clamp circuit into the analog I/O pin, the device dimension (W/L) of ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (μm/μm) in a 0.35-μm silicided CMOS process, but it can sustain the human-body-model (machine-model) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only ～1.0 pF (including the bond pad capacitance) for high-frequency applications. A design model to find the optimized layout dimensions and spacings on the input ESD clamp devices has been also developed to keep the total input capacitance almost constant (within 1% variation), even if the analog input signal has a dynamic range of 1 V. Key Words: electrostatic discharge (ESD), ESD protection circuit, input capacitance, analog pin 1. Introduction Electrostatic discharge (ESD) has been the main reli- ability concern on semiconductor products, especially in the scaled-down CMOS technologies [1,2]. Due to the low breakdown voltage of the thinner gate oxide in deep-submicron CMOS technologies, an efficient ESD protection circuit should be designed and placed on ev- ery input