ISO-CMOSST-BUSFAMILYMT8920B.PDFVIP

?Ordering Information MT8920BE 28 Pin Plastic DIP MT8920BC 28 Pin Ceramic DIP MT8920BP 28 Pin Plastic J-Lead MT8920BS 28 Pin SOIC -40°C to 85°C ISSUE 6 June 1996Figure 1 - Functional Block Diagram D7-D0 A4-A0 CS DS, OE R/W, WE DTACK, BUSY, DCS IRQ, 24/32 IACK, MS1 A5, STCH MMS V SS V DD C4i F0i STo1 STi0 STo0 Tx0 Dual Port Ram 32 X 8 Rx0 Dual Port Ram 32 X 8 Tx1 Dual Port Ram 32 X 8 Parallel- to-serial Converter Serial-to- Parallel Converter Parallel- to-Serial Converter Comp/ MUX Address Generator Parallel Port Interface Interrupt Registers Control RegistersMT8920B ST-BUS Parallel Access Circuit ISO-CMOS ST-BUS? FAMILYFeatures ? High speed parallel access to the serial ST-BUS ? Parallel bus optimized for 68000 μP (mode 1) ? Fast dual-port RAM access (mode 2) Access time: 120 nsec ? Parallel bus controller (mode 3) - no external controller required ? Flexible interrupt capabilities - two independent/programmable interrupt sources with auto-vectoring ? Selectable 24 and 32 channel operation ? Programmable loop-around modes ? Low power CMOS technology Applications ? Parallel control/data access to T1/CEPT digital trunk interfaces ? Digital signal processor interface to ST-BUS ? Computer to Digital PABX link ? Voice store and forward systems ? Interprocessor communications Description The ST-BUS Parallel Access Circuit (STPA) provides a simple interface between Mitel’s ST-BUS and parallel system environments.33- MT8920B CMOSFigure 2 - Pin Connections Pin Description Pin # Name Description ? 1 C4i 4.096 MHz Clock. The ST-BUS timing clock used to establish bit cell boundaries for the serial bus. 2 F0i Framing Pulse. A low going pulse used to synchronize the STPA to the 2048 kbit/s ST-BUS stream. The first falling edge of C4i subsequent to the falling edge of F0i identifies the start of a frame. 3 IACK Interrupt Acknowledge (Mode 1). This active low input signals that the current bus cycle is an interrupt vector fetch cycle. Upon receiving this ackn