83020012A,SNJ54ALS373AFK, 规格书,Datasheet 资料.pdfVIP

SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS083C – APRIL 1982 – REVISED MARCH 2002 1POST OFFICE BOX 655303 ? DALLAS, TEXAS 75265 Eight Latches in a Single Package 3-State Bus-Driving True Outputs Full Parallel Access for Loading Buffered Control Inputs pnp Inputs Reduce dc Loading on Data Lines description These octal transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off. Copyright ? 2002, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND V CC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE SN54ALS373A, . . . J OR W PACKAGE SN54AS