Pm25LD256C datasheet v0.5.pdf

Pm25LD256C Chingis Technology Corp. 1 DRAFT Date: November, 2010, Rev: 0.5 FEATURES ? Single Power Supply Operation - Low voltage range: 2.7 V - 3.6 V ? Memory Organization - Pm25LD256C: 32K x 8 (256Kbit) ? Cost Effective Sector/Block Architecture -256Kb : Uniform 4KByte sectors / one uniform 32KByte blocks ? Low standby current 1uA (Typ) ? Serial Peripheral Interface (SPI) Compatible - Supports single- or dual-output - Supports SPI Modes 0 and 3 - Maximum 33 MHz clock rate for normal read - Maximum 100 MHz clock rate for fast read ? Page Program (up to 256 Bytes) Operation - Typical 2 ms per page program ? Sector, Block or Chip Erase Operation - Maximum 7 ms sector, block or chip erase ? Low Power Consumption - Typical 1 mA active read current - Typical 10 mA program/erase current ? Hardware Write Protection - Protect and unprotect the device from write operation by Write Protect (WP#) Pin ? Software Write Protection - The Block Protect (BP2, BP1, BP0) bits allow partial or entire memory to be configured as read- only ? High Product Endurance - Guaranteed 200,000 program/erase cycles per single sector - Minimum 20 years data retention ? Industrial Standard Pin-out and Package - 8-pin 150mil SOIC - 8-pin TSSOP - Lead-free (Pb-free), halogen-free package GENERAL DESCRIPTION The Pm25LD256C are 256Kbit Serial Peripheral Interface (SPI) Flash memories, providing single- or dual- output. The devices are designed to support a 33 MHz clock rate in normal read mode, and 100 MHz in fast read, the fastest in the industry. The devices use a single low voltage power supply, wide o