40nm-gate-sb-p-channel-guide.pdf

1High-Performance 40nm Gate Length InSb P-Channel Compressively Strained Quantum Well Field Effect Transistors for Low-Power (VCC=0.5V) Logic Applications M. Radosavljevic, T. Ashley*, A. Andreev*, S. D. Coomber*, G. Dewey, M. T. Emeny*, M. Fearn*, D. G. Hayes*, K. P. Hilton*, M. K. Hudait, R. Jefferies*, T. Martin*, R. Pillarisetty, W. Rachmady, T. Rakshit, S. J. Smith*, M. J. Uren*, D. J. Wallis*, P. J. Wilding* and Robert Chau Components Research, TMG Intel Corporation *QinetiQ Contact: robert.s.chau@ 2Outline ?Motivation ?Materials ?Transistors ?Benchmarking ?Summary 3?Motivation ?Materials ?Transistors ?Benchmarking ?Summary Outline 4? III-V n-channel has 30X higher electron mobility over Si ? III-V on Si achieves fT 400GHz at VCC=0.5V * 5x1011 1012 1013 2x1013 102 103 104 105 E L E C T R O N M O B I L I T Y [ c m 2 / V s ] SHEET CARRIER DENSITY [cm-2] Si InGaAs InSb 30X improvement Advantages of III-V n-QWFETs for Low VCC Logic (e.g. 0.5V) 10 100 1000 0 100 200 300 400 500 C U T - O F F F R E Q U E N C Y , f T [ G H Z ] DC POWER DISSIPATION [?W/?m] InSb n-QWFET on Si (LG=85nm) InGaAs n-QWFET on Si (LG=80nm) VCC = 0.5V Silicon (LG=60nm) VCC = 0.5V VCC = 1.1V C U T - O F F F R E Q U E N C Y , f T [ G H Z ] 5Measurement Data at VG-VT=0.3V 5X↑ ? Veff=Gmi/Cgi, extracted from RF measurements ? Further improvement in Veff via shorter gate-to-QW separation and continued LG scaling Advantages of III-V n-QWFETs for Low VCC Logic (e.g. 0.5V) 60 0.2 0.4 0.6 0.8 1 1.2 -20 0 20 40 60 80 0 0.2 0.4 0.6 0.8 I n t r i n s i c D r i v e C u r r e n t ( m A / ? m ) % G ain III-V over Silicon Gate Overdrive (V G -V T ) (Volt) Strained Si (T OXE =14A) InGaAs QWFET (T OXE =34A) SS=90mV/dec DIBL=150mV/V V DS =0.5V 0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.1 0.2 0.3 0.4 0.5 D r a i n c u r r e n t , I D ( m A / ? m ) Drain voltage, V DS (V) V G -V T =0.3V 80nm InGaAs QW, TOXE=27A RSD matched to Si (Simulated) 80nm InGaAs QW TOXE=34A 40nm Strained Si TOX