Analog Soft-Pattern-Matching Classifier Using Floating-Gate.pdf

Analog Soft-Pattern-Matching Classifier using Floating-Gate MOS Technology Toshihiko YAMASAKI and Tadashi SHIBATA* Department of Electronic Engineering, School of Eng ineering *Department of Frontier Informatics, School of Fron tier Science The University of Tokyo 7-3-1 Hongo, Bunkyo-ku, Tokyo, 113-8656, Japan yamasaki@if.t.u-tokyo.ac.jp, shibata@ee.t.u-tokyo.a c.jp Abstract A flexible pattern-matching analog classifier is pr esented in con- junction with a robust image representation algorit hm called Prin- cipal Axes Projection (PAP). In the circuit, the fu nctional form of matching is configurable in terms of the peak posit ion, the peak height and the sharpness of the similarity evaluation. The test chip was fabri- cated in a 0.6- μm CMOS technology and successfully applied to hand-written pattern recognition and medical radiog raph analysis using PAP as afeature xtraction pre-processing step for robust image coding. The separation and classification of overlapping pa tterns is also ex- perimentally demonstrated. 1 Introduction Pattern classification using template matching tech niques is a powerful tool in im- plementing human-like intelligent systems. However, the processing is computa- tionally very expensive, consuming a lot of CPU time when implemented as of t- ware running on general-purpose computers. Therefor e, software approaches are not practical for eal-time applications. For systems working in mobile nviron ment, in particular, they are not realistic because the memory and computational resources are severely limited. The development of analog VLS I chips having afully parallel template matching architecture [1,2] would be apro mising solution in such applica- tions because they offer an opportunity of low-power operation as well as very compact implementation. In order to build areal human-like intelligent sys tem, however, not only the pattern representation algorithm but also the matching hard ware itself needs to