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Calibration of Rent’s Rule Models for Three-Dimensional Integrated Circuits.pdf

Calibration of Rent’s Rule Models for Three-Dimensional Integrated Circuits.pdf

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Calibration of Rent’s Rule Models for Three-Dimensional Integrated Circuits

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 4, APRIL 2004 359 Calibration of Rent’s Rule Models for Three-Dimensional Integrated Circuits Shamik Das, Member, IEEE, Anantha P. Chandrakasan, Fellow, IEEE, and Rafael Reif, Fellow, IEEE Abstract—In this paper, we determine the accuracy of Rahman’s interconnect prediction model for three-dimensional (3-D) integrated circuits. Utilizing this model, we calculate the wiring requirement for a set of benchmark standard-cell circuits. We then obtain placed and routed wirelength figures for these circuits using 3-D standard-cell placement and global-routing tools we have developed. We find that the Rahman model predicts wirelengths accurately (to within 20% of placement and of routing, on average), and suggest some areas for minor improvement to the model. Index Terms—Rent’s Rule, system-level interconnect prediction (SLIP), three-dimensional (3-D) integration. I. INTRODUCTION T ECHNOLOGY feature sizes continue to shrink to meetperformance demands on integrated circuits. This, cou- pled with growing overall chip dimensions, leads to greater con- sumption of the available power and delay budgets by the inter- connect structures on these chips [2]. As global and semiglobal wires become increasingly expensive and clock frequencies be- come higher and higher, designers seek new architectures and technologies that rely less on sending signals across the chip [3]. However, few scalable solutions have been proposed. One such solution is three-dimensional (3-D) integration. In a 3-D integrated circuit, transistors may be fabricated on top of other transistors, resulting in multiple layers of active compo- nents. These transistors may then be wired to other transistors on the same device layer, to transistors on different device layers, or both, depending on the process technology. Several different approaches to fabricating 3-D circuits or 3-D-compatible tran- sistors have been taken [4]–[7]. These va

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