Method to suppress DDFS spurious signals in a frequency-hopping synthesizer with DDFS-driven PLL.pdfVIP

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Method to suppress DDFS spurious signals in a frequency-hopping synthesizer with DDFS-driven PLL.pdf

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Method to suppress DDFS spurious signals in a frequency-hopping synthesizer with DDFS-driven PLL

0885–3010/$25.00 ? 2010 IEEE 299IEEE TransacTIons on UlTrasonIcs, FErroElEcTrIcs, and FrEqUEncy conTrol, vol. 57, no. 2, FEbrUary 2010 Abstract—In this paper we propose a method of remov- ing from synthesizer output spurious signals due to quasi-am- plitude modulation and superposition effect in a frequency- hopping synthesizer with direct digital frequency synthesizer (DDFS)-driven phase-locked loop (PLL) architecture, which has the advantages of high frequency resolution, fast transition time, and small size. There are spurious signals that depend on normalized frequency of DDFS. They can be dominant if they occur within the PLL loop bandwidth. We suggest that such signals can be eliminated by purposefully creating frequency errors in the developed synthesizer. I. Introduction as a result of the steady requirement for small-size, lightweight, and power-efficient communication sys- tems, the application of direct digital frequency synthe- sizers (ddFs) to synthesizers is increasing in spite of its various spurious signals. all ddFss based on a binary system synthesize the output frequency by using a sampling theorem, and their spurious signals can be classified into 4 groups according to their sources, which have been analyzed in many previ- ous studies [1]–[4]. The major sources of spurious signals are phase truncation, the limited length in sine look-up tables, the finite resolution of digital-to-analog converter (dac), and intermodulation problems (see Fig. 1). Whereas these sources depend on a specification of the ddFs hardware, there are other sources of spurious sig- nals that are related to only the normalized frequency of the ddFs. Here, we encounter quasi-amplitude modula- tion and superposition effect [5]. When we first designed a frequency synthesizer with ddFs-driven phase-locked loop (Pll) architecture, we were able to predict to some extent the output level of the spurious signals from 4 sources, because the levels of spurious sign