Lecture17Adders.pptVIP

* * * * * * * * * * * 17: Adders * Tree Adder Taxonomy 17: Adders * Han-Carlson 17: Adders * Knowles [2, 1, 1, 1] 17: Adders * Ladner-Fischer 17: Adders * Taxonomy Revisited 17: Adders * Summary Architecture Classification Logic Levels Max Fanout Tracks Cells Carry-Ripple N-1 1 1 N Carry-Skip n=4 N/4 + 5 2 1 1.25N Carry-Inc. n=4 N/4 + 2 4 1 2N Brent-Kung (L-1, 0, 0) 2log2N – 1 2 1 2N Sklansky (0, L-1, 0) log2N N/2 + 1 1 0.5 Nlog2N Kogge-Stone (0, 0, L-1) log2N 2 N/2 Nlog2N Adder architectures offer area / power / delay tradeoffs. Choose the best one for your application. * * * * * * * * * * * * * * * * * * * * * * * * * * 17: Adders CMOS VLSI Design CMOS VLSI Design 4th Ed. Lecture 17: Adders 17: Adders * Outline Single-bit Addition Carry-Ripple Adder Carry-Skip Adder Carry-Lookahead Adder Carry-Select Adder Carry-Increment Adder Tree Adder 17: Adders * Single-Bit Addition Half Adder Full Adder A B Cout S 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 A B C Cout S 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 17: Adders * PGK For a full adder, define what happens to carries (in terms of A and B) Generate: Cout = 1 independent of C G = A ? B Propagate: Cout = C P = A ? B Kill: Cout = 0 independent of C K = ~A ? ~B 17: Adders * Full Adder Design I Brute force implementation from eqns 17: Adders * Full Adder Design II Factor S in terms of Cout S = ABC + (A + B + C)(~Cout) Critical path is usually C to Cout in ripple adder 17: Adders * Layout Clever layout circumvents usual line of diffusion Use wide transistors on critical path Eliminate output inverters 17: Adders * Full Adder Design III Complementary Pass Transistor Logic (CPL) Slightly faster, but more area 17: Adders * Full Adder Design IV Dual-rail domino Very fast, but large and power hungry Used in very fast multipliers 17: Adders * Carry Propagate Adders N-bit adder called CPA Each sum bit depends on all previous carries How do we compute all these carries quickl