如何构建1-bit-widemux.ppt

CS61C L221 Performance ? UC Regents Review Use this table and techniques we learned to transform from 1 to another Today Data Multiplexors Arithmetic and Logic Unit Adder/Subtractor Data Multiplexor (here 2-to-1, n-bit-wide) N 个1-bit-wide mux 如何构建 1-bit-wide mux? 4-to-1 Multiplexor? 其它方式完成? 算术逻辑单元Arithmetic and Logic Unit 大多数处理器都包含一个称为算术逻辑单元的逻辑块 “Arithmetic and Logic Unit” (ALU) 下面将讲授进行加(ADD), 减(SUB), 按位与(AND), 按位或(bitwise OR) Our simple ALU 加/减法设计 – 如何进行? 真值表, 然后确定与或范式, 然后简化 将问题分解为更小的问题，使用层次方法或者连接的方法进行求解 Adder/Subtracter – One-bit adder LSB… Adder/Subtracter – One-bit adder (1/2)… Adder/Subtracter – One-bit adder (2/2)… N 1-bit adders ? 1 N-bit adder What about overflow? 表示: 数 正数　反　补 　 -2 10 　01 10 -1 01　 10 11 0 00 1 01 关于溢出(overflow)? 考虑二位有符号数加法及溢出 overflow: 10 = -2 + -2 or -1 11 = -1 + -2 only 00 = 0 NOTHING! 01 = 1 + 1 only Highest adder C1 = Carry-in = Cin, C2 = Carry-out = Cout 10 10 01 10 10 01 01 11 11 00 10 11 01 00 01 00 11 11 00 00 10 10 01 00 00 00 11 11 00 00 Cin but no Cout Cout but no Cin What about overflow? Consider a 2-bit signed # overflow: 10 = -2 + -2 or -111 = -1 + -2 only00 = 0 NOTHING!01 = 1 + 1 only Overflows when… Cin, but no Cout ? A,B both 0, overflow! Cout, but no Cin ? A,B both 0, overflow! Overflow detection?　Another explain Extremely Clever Subtractor Peer Instruction Truth table for mux with 4-bits of signals has 24 rows We could cascade N 1-bit shifters to make 1 N-bit shifter for sll, srl If 1-bit adder delay is T, the N-bit adder delay would also be T Peer Instruction Answer Truth table for mux with 4-bits of signals is 24 rows long We could cascade N 1-bit shifters to make 1 N-bit shifter for sll, srl If 1-bit adder delay is T, the N-bit adder delay would also be T “And In conclusion…” Use muxes to select among input S input bits selects 2S inputs Each input can be n-bits wide, indep of S Implement muxes hierarchically ALU can be implemented using a mux Coupled with