位除位有符号数的VHDL设计.docVIP

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; Entity Divider is port( clk: in std_logic; --reset: in std_logic; start: in std_logic; word1: in std_logic_vector(15 downto 0);--被除数 word2: in std_logic_vector(7 downto 0);--除数 data_out: out std_logic_vector(15 downto 0)--商 ); end Divider; Architecture Divider_arc of Divider is type states is(S_Idle,S_Adivr,S_Adivn,S_div); signal state,next_state:states; signal dividend:std_logic_vector(16 downto 0); signal comparison:std_logic_vector(8 downto 0); signal divisor:std_logic_vector(7 downto 0); signal load_words,shift_divisor,shift_dividend,subtract:std_logic; signal num_shift_divisor,num_shift_dividend:integer range 0 to 16; signal quotient:std_logic_vector(15 downto 0); begin process(state,dividend,divisor) begin case state is when S_Adivr = if divisor(7)=0 then comparison=1(not(divisor(6 downto 0)0)) +000000001+dividend(16 downto 8); else comparison=1(not divisor) +000000001+dividend(16 downto 8); end if; when others = comparison=1(not divisor) +000000001+dividend(16 downto 8); end case; end process; process(clk,start) begin if start=1 then state=S_idle; elsif clkevent and clk=1 then state=next_state; end if; end process; process(state,word1,word2,divisor,comparison,num_shift_divisor,num_shift_dividend) begin Load_words=0;Shift_dividend=0;Shift_divisor=0;Subtract=0; case state is when S_Idle=--case start is --when 0=next_state=S_idle; --when 1= if word2then next_state=S_idle; elsif word1=0000000000000000 then next_state=S_idle; else next_state=S_Adivr;Load_words=1; end if; --end case; when S_Adivr= case divisor(7) is when 1=next_state=S_div; when 0=if comparison(8)=0 then next_state=S_adivr;shift_divisor=1; elsif comparison(8)=1 then next_state=S_Adivn; end if; end case; when S_Adivn= if num_shift