数字集成电路可测性设计及验证方法学.ppt

* 共102页 * PrimeTime脚本— source pt.scr set_operating_conditions -min_library scc65nll_hs_rvt_ff_v1p32_-40c_basic -min ff_v1p32_-40c -max_library scc65nll_hs_rvt_ss_v1p08_125c_basic -max ss_v1p08_125c -analysis_type bc_wcset_operating_conditions -library scc65nll_hs_rvt_ff_v1p32_-40c_basic ff_v1p32_-40c create_clock -name clk -period 300 -waveform [list 0 150] clk_in_pad set_clock_latency 2.0 [all_clocks] set_clock_uncertainty -setup 2.0 clk set_clock_transition 2 [get_clocks clk] set_drive 0 [list clk clk_in_pad ] set_driving_cell -library SP65NLLD2RP_OV3_TTM_V0p2_ss_V1p08_125C -lib_cell PICDR -pin C [remove_from_collection [all_inputs] [get_ports {clk_in_pad}]] set_load 2 [all_outputs] set_input_delay 5 -clock clk -max [remove_from_collection [all_inputs] [get_ports {clk_in_pad}] ] set_output_delay 5 -clock clk -max [all_outputs] report_constraint report_timing 形式验证--Formality 所谓形式验证，就是通过比较两个设计在逻辑功能是否等同的方法来验证电路的功能。 Formality是Synopsys公司的产品，与PrimeTime结合起来使用。 * 共102页 * Formality流程 1.设置环境 2.创建container 3.读入库文件 4.读入设计文件 5.定义参考库和设计库 6.连接 7.开始比较 * 共102页 * Formality工具启动 source /opt/demo/synopsys.env fm_shell formality * 共102页 * * 共102页 * 命令输入区 * 共102页 * Formality— source fm.scr set lib_path /home1t/smic/smic_65/SCC65NLL_HS_RVT_V1p1aset smic_stdlib_path ${lib_path}/synopsys/1.2v/set smic_diolib_path /home1t/smic/smic_65/SP65NLLD2RP_OV3_TTM_V0p2a/syn/3p3v/set smic_aiolib_path /home1t/smic/smic_65/SP65NLLD2RP_OV3_ANALOG_TTM_V0p2a/syn/3p3v/set search_path $smic_stdlib_path $smic_aiolib_path $smic_diolib_path create_container ref read_db [list scc65nll_hs_rvt_ss_v1p08_125c_basic.db \SP65NLLD2RP_OV3_TTM_V0p2_ss_V1p08_125C.db \SP65NLLD2RP_OV3_ANALOG_TTM_V0p1_ss_v1p08_125C.db] read_verilog {../rtl/dac_haf_cic/top.v \ ../rtl/dac_haf_cic/filter.v \ ../rtl/dac_haf_cic/en.v \ ../rtl/dac_haf_cic/haf1_new.v \ ../rtl/dac_haf_cic/haf2_new.v \ ../rtl/dac_haf_cic/Hcic.v \ ../rtl/dac_haf_cic/modulator.v \ ../rtl/dac_haf_cic/DWA.v} * 共102页 * Formality— source fm.scr set_refer