王前-数字系统设计-2.4 VHDL主要描述方式.pptVIP

2.4 VHDL主要描述方式;VHDL主要描述方式;行为描述方式;行为描述方式;数据流描述方式; ;半加器;全加器;全加器;元件例化语句;练习题;entity And2 is port (x, y : in bit; z: out bit); end And2; architecture ex1 of And2 is begin z = x and y; end ex1; ;entity Or2 is port (x, y : in bit; z: out bit); end entity Or2; architecture ex1 of Or2 is begin z = x or y; end architecture ex1; ;entity Not1 is port (x : in bit; z: out bit); end entity Not1; architecture ex1 of Not1 is begin z = not x; end architecture ex1; ;entity comb_function is port (a, b, c : in bit; z: out bit); end entity comb_function; architecture netlist of co