FE1.1s (B) Data Sheet 0.1.pdf

USB 2.0 4-Port Hub Data Sheet Rev. B0.1 FE1.1S – REVISION B USB 2.0 HIGH SPEED 4-PORT HUB CONTROLLER _______________________Data Sheet_______________________ INTRODUCTION The FE1.1s is a highly integrated, high quality, high performance, low power consumption, yet low cost solution for USB 4-Port Hub. It is fully compliant to “Universal Serial Bus Specification Revision 2.0”, and supports USB-IF “Battery Charging Specification Revision 1.1”. It adopts Single Transaction Translator (STT) architecture to be more cost effective. Six, instead of two, non-periodic transaction buffers are used to minimize potential traffic jamming. The whole design is based on state-machine- control to reduce the response delay time; no micro controller is used in this chip. To guarantee high quality, the whole chip is covered by Test Scan Chain – even on the high speed (480MHz) modules, so that all the logic components could be fully tested before shipping. Special Build-In-Self-Test mode is designed to exercise all high, full, and low speed Analog Front End (AFE) components on the packaging and testing stages as well. Low power consumption is achieved by using advanced technology and comprehensive power/clock control mechanism. FE1.1s could be optionally configured to support Charging Downstream Ports as defined by the USB-IF Battery Charging Specification. With this feature enabled, an USB hub could be easily transformed into a charging station for battery based portable devices. FEATURES ? Fully compliant with Universal Serial Bus Specification Revision 2.0 (USB 2.0); □ Upstream facing port supports High- Speed (480MHz) and Full-Speed (12MHz) modes; □ 4 downstream facing ports support High-Speed (480MHz), Full-Speed (12MHz), and Low-Speed (1.5MHz) modes; ? Integrated USB 2.0 Transceivers; ? Integrated upstream 1.5KΩ pull-up, downstream 15KΩ pull-down, and serial resisters; ? Integrated 5V to 3.3V and 1.8V regulator. ? Integrated Power-On-Reset circui