High-speed, burst-mode, packet-capable optical receiver and instantaneous clock recovery for optical.pdfVIP

JOURNAL OF LIGHTWAVE TECHNOLOGY, VOL. 12, NO. 2, FEBRUARY 1994 325 High-speed, Burst-Mode, Packet-Capable Optical Receiver and Instantaneous Clock Recovery for Optical Bus Operation Yusuke Ota, Robert G. Swartz, Fellow, IEEE, Vance D. Archer 111, Member, IEEE, Steven K. Korotky, Mihai Banu, and Alfred E. Dunlop, Fellow, IEEE Abstract-This paper describes an enhanced performance ver- sion of a high-speed burst-mode compatible optical receiver and its application to 622-Mbls optical bus operation in conjunction with an instantaneous clock recovery scheme. The receiver is fabricated in a 12 GHz ft silicon bipolar technology and consists of a differential transimpedance amplifier with an auto-threshold level controller and a high-speed quantizer. Using an InGaAs avalanche photodiode, the typical burst mode sensitivity is around -34 dBm BER) at bit rates up to 1.5 Gbls with a dynamic range of 26 dB for both pseudorandom and burst signals. The results using a laser beam modulated by a high-speed external modulator indicate that the receiver can be operated at bit rates higher than 2 Gb/s. With a worst-case self-resetting time 50 ns for the threshold control circuit, the receiver is usable for optical packet communication where data signals with varying optical power are employed. This receiver was demonstrated in a 622-Mb/s optical bus application where the clock signal was recovered from the packet data signal using a novel high-speed CMOS instantaneous clock recovery IC. I. INTRODUCTION HARED bus optical applications employ short bursts or S packets of digital data. Conventional AC-coupled fiber- optic receivers, intended for continuous data reception, are un- usable in such applications unless data encoding is employed to add frequent artificial transitions. But data encoding is insufficient in a bus-type environment where the transmission medium is shared among many sources. Recently, we have reported DC-coupled receiver architectures