Lab05 - Connect Hardware 2013_3_02.pdfVIP

Copyright ? 2013 Avnet Inc. All rights reserved Developing Zynq Software with Xilinx SDK Lab 5 Connecting SDK to Hardware November 2013 Version 02 ZedBoard Lab 5 : 2 Lab 5 Overview At last we will now be able to power up the Zynq hardware. Using the example application projects and the SDK, we will connect to the hardware through a JTAG connection. The bitstream will be programmed into the PL, the ARM processor configured, and the code bootloaded to the appropriate memory. SDK can be used to simply run the application or use a full-featured application debugger to step through the code. Lab 5 Objectives When you have completed Lab 5, you will know how to: ? Set up the hardware for operation ? Program a bitstream to the PL ? Configure the ARM PS over JTAG using TCL ? Run an application ? Debug an application ZedBoard Lab 5 : 3 Experiment 1: Setup Hardware and Download Bitstream Xilinx Zynq SoCs are SRAM-based devices, meaning they are volatile. The PL is volatile and the ARM registers are also volatile. In production, the PL hardware definition (or bitstream) and the ARM PS configuration code (or First-Stage Boot Loader FSBL) are stored in Flash on the board, such as a Quad-SPI Flash or SD Card. Before storing a hardware/software design to Flash, developers will want to experiment with the code – both PL hardware code as well as software application code. In this experiment, we will focus on software application code experimentation directly from SDK. Making use of a JTAG connection to the hardware, SDK will be able to perform all the functions that would normally be performed from Flash. The SDK-SoC JTAG interface may be used to accomplish all these things: ? Read and write ARM registers ? Configure the PL with a bitstream ? Program attached QSPI Flash ? Upload application code to on-chip RAM or DDR3 ? Application debug ZedBoard Lab 5 : 4 Experiment 1 General Instruction: