Lecture-02_MOS-IV.pdfVIP

EE115C – Spring 2013 Digital Electronic Circuits Lecture 2: MOS Transistor: IV Model Levels of Modeling Analytical CAD analytical Switch-level sim Transistor-level sim complexity Different complexity, accuracy, speed of convergence… EE115C – Spring 2013 2 MOS Transistor Modeling Our goal is to model delay and energy not current But have to start with current D S EE115C – Spring 2013 3 MOSFET, Notations D S G B Leff Ld xdxd tox L = LeffHand-analysis I-V formulas: EE115C – Spring 2013 4 Important Concepts to Understand ? Threshold voltage (VT) ? Velocity saturation ? Channel length modulation (channel pinch-off) EE115C – Spring 2013 5 Threshold Voltage, VT NMOS: ? VSB 0 (RBB) ? VSB 0 (FBB) PMOS: ? VSB 0 (FBB) ? VSB 0 (RBB) ???? = ?????? + ?? ? ( | ? ?????? + ??????| ? |??????|) B G D S VSB VT VSB = 0 VT0 is approx 0.2V for our process EE115C – Spring 2013 6 Outline ?MOS Transistor – Basic Operation – Modes of Operation – Deep sub-micron MOS EE115C – Spring 2013 7 The Drain Current in Linear Regime ? Combining velocity and charge: ? Integrating over the channel: Transconductance: Gain factor: Small VDS ? ignore quadratic term ? linear VDS dependence L = effective L = Ld – 2xd EE115C – Spring 2013 8 Velocity Saturation ? Carrier velocity saturates when critical field is reached v ε vsat 105 m/s με εc EE115C – Spring 2013 9 Simple Model EE115C – Spring 2013 10 A More General Model In deep submicron, there are four regions of operation: (1) cutoff, (2) resistive, (3) saturation and (4) velocity saturation ? Approximate velocity: for ξ ≤ ξc for ξ ≥ ξc ? And integrate current again: A more general model: we use n = 1 EE115C – Spring 2013 11 Including Velocity Saturation in the ID Formula EE115C – Spring 2013 12 Calculating Velocity Saturation, VDSAT EE115C – Spring 2013 13 Vsat Occurs at LOWER VDS than Sat SatVsat ID VDS k VDS = VGTVDS = k·VGT ?? = ?? ?? + ?????? ???? ? ?? k = k(VGT) EE115C – Spring 2013 14 Vsat: Less Current for Same VGS Sat (Long-L) Vsat (Short-L)