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MDCSIM A COMPILED EVENT-DRIVEN MULTI- DELAY SIMULATOR
MDCSIM: A COMPILED EVENT-DRIVEN MULTI-
DELAY SIMULATOR
Yun-Sik Lee
Peter M. Maurer
Department of Computer Science and Engineering
University of South Florida
Tampa, FL 33620
MDCSIM: A COMPILED EVENT-DRIVEN MULTI-
DELAY SIMULATOR
ABSTRACT
This paper describes a complied event driven logic simulator which allows gates to have delays that
are integral multiples of some basic time unit. The nets and gates of a circuit are compiled into a routines
that perform the evaluation of gates and process events. These routines also manage the current timing
wheel slot and insert events into the appropriate future time slots. A threaded code implementation is used
to reduce execution time and space. Experimental results have shown a 26% improvement in execution
time for compiled simulation over a standard event driven simulator.
MDCSIM: A COMPILED EVENT-DRIVEN MULTI-
DELAY SIMULATOR
Introduction.
As the design of a circuit proceeds, it is necessary to simulate circuits behavior more and more
accurately. In particular, more and more accurate timing models are needed. During the final phases of the
design it is usually necessary to deal with the delays of the individual elements more accurately than is
possible with a unit-delay or zero-delay simulator. Recently there has been much renewed interest in
compiled simulation, particularly because it promises to provide better performance than is normally
provided by interpreted simulators[1-9]. Although there are many well-known compiled simulation
algorithms, these are based on the zero delay or the unit delay timing models. These timing models do not
provide an accurate model of the circuits timing behavior. For some circuit elements, such as delay lines,
multivibrators and inverters, delay is the essential nature of their function, and a reasonably accurate timing
model is necessary to model their behavior.
This paper focuses on the multi-delay timing model, in which the delay of each gate is modeled as an
integral multipl
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