MICROARCHITECTURES GIVEN ROUTER PARAMETERS, THIS DELAY MODEL PRESCRIBES REALISTIC PIPELINES.pdfVIP

MICROARCHITECTURES GIVEN ROUTER PARAMETERS, THIS DELAY MODEL PRESCRIBES REALISTIC PIPELINES.pdf

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MICROARCHITECTURES GIVEN ROUTER PARAMETERS, THIS DELAY MODEL PRESCRIBES REALISTIC PIPELINES

26 Buses and crossbars have tradition- ally served as the communication fabrics of computer systems, network switches and routers, and other digital systems. However, demand for communication bandwidth is overwhelming the limits of these fabrics, and interconnection networks, historically used in high-end multiprocessor systems,1-3 have sur- faced as an alternative. In recent years, inter- connection network fabrics have been deployed in high-speed network switches4 and high-bandwidth core Internet routers.5 These interconnection networks’ perfor- mance critically depends on the performance of the routers from which they are construct- ed. Armed with accurate router performance models, interconnection network architects can optimize and fine-tune router parameters before starting detailed design. This article introduces a router delay model that takes into account the pipelined nature of contemporary routers and proposes pipelines matched to the specific flow control method employed. Given the type of flow control (see the “What is flow control?” side- bar) and router parameters, the model returns router latency in technology-independent units and the number of pipeline stages as a function of cycle time. We apply this model to derive realistic pipelines for wormhole and virtual-channel routers and compare their performance. Con- trary to the conclusions of previous models, our results show that the latency of a virtual- channel router doesn’t increase as we scale the number of virtual channels up to 8 per phys- ical channel. Our simulation results also show that a virtual-channel router gains through- put of up to 40% over a wormhole router. Compared with the commonly assumed unit-latency model, which ignores imple- mentation complexity and assumes router latency to be a single cycle, our model shows significant performance differences: 56% in zero-load latency and 30% in throughput. This highlights the importance of consider- ing implementation costs when simulati

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