集成电路设计-10-系统设计-3重点.pptVIP

集成电路设计;纲要;1.概述 ——The Design Productivity Challenge;A Simple Processor;A System-on-a-Chip: Example;can be implemented with： Hardware processor + suitable software programs (flexibility) a. Pentium IV + suitable software programs (high-level language) b. TI-DSP + suitable software programs c. MCU(8051) + suitable software programs (low-level language) Dedicated hardware circuits (faster) a. old_PCBs (TTL SSI, MSI chips and wires) b. new_PCBs(some devices, application specific integrated circuit-ASIC, wires) Some hardware circuits + software programs (to solve more complex problems) a. System on a board (memory, processor, ASIC, I/O, other devices) b. System on a chip (SoC) current and future work;Hierarchical Components in PCB ; Choose the design entry method: Schematic Gate level design Intuitive easy to debug HDL (Hardware Description Language) Descriptive portable Easy to modify Mixed HDL Schematic …;2.实现方法Implementation Choices;The Custom Approach ;Full Custom Design;Transition to Automation and Regular Structures;Semi Custom Design;3.基于单元的设计 Cell-based Design (or standard cells);Cells are characterized and stored in library Need update when technology advance Need technology mapping before layout for each design;Standard Cell — Example;Standard Cell – The New Generation;Standard Cell - Example;PLA- Programble Logic Array;Two-Level Logic;PLA Layout – Exploiting Regularity;复杂性超过单元库中单元的程度 Megacell（巨单元） Hard—具有指定功能，及预先确定的物理设计。 Soft —具有指定功能，但无预先确定的物理设计。;hard-macro Modules;“Soft” MacroModules;Inside the 22v10 “Macrocell” Block;Input/Output Equivalent Schematics;“Intellectual Property”;4. Semicustom（半定制 ）Design Flow;时序最终确定The “Design Closure(设计收敛)” Problem;Integrating Synthesis with Physical Design;;预扩散（掩模）阵列 Gate Array （ Sea-of-gates）;门海Sea-of-gate ;Sea-of-gates;预布线阵列Prewired Arrays;Fuse-Based FPGA;Programmable Array Logic (PAL) ;Array-Based Programmable Logic Device（PLD）;Pro