EDA原理第十一章数字时钟设计.ppt

数字时钟设计及实现 ;数字时钟设计-本章概要; 数字时钟设计-数字时钟的功能要求 ; 数字时钟设计-数字时钟的结构; 数字时钟设计-数字时钟的结构;数字时钟设计-控制模块结构; 数字时钟设计-控制模块结构; 数字时钟设计-控制模块结构; 数字时钟设计-控制模块结构; 数字时钟设计-控制模块结构; 数字时钟设计-控制模块结构; 数字时钟设计-控制模块结构; 数字时钟设计-控制模块结构;数字时钟设计-控制模块结构;数字时钟设计-控制模块结构;数字时钟设计-控制模块结构; 数字时钟设计-主程序;--信号定义： architecture Behavioral of clock is signal sec_counter1:std_logic_vector(3 downto 0); signal sec_counter2:std_logic_vector(3 downto 0); signal min_counter1:std_logic_vector(3 downto 0); signal min_counter2:std_logic_vector(3 downto 0); signal hour_counter1:std_logic_vector(3 downto 0); signal hour_counter2:std_logic_vector(3 downto 0); signal divcounter : std_logic_vector(3 downto 0); signal div_clk : std_logic; signal scancounter : std_logic_vector(1 downto 0); signal scan_clk : std_logic; signal scan_out : std_logic_vector(2 downto 0); signal secseg1,secseg2,minseg1,minseg2,hourseg1,hourseg2:std_logic_vector(7 downto 0); begin;--计数时钟，对外部输入时钟分频，此处只适用于仿真，实际进行时间计数时，分频后时钟应该满足1HZ。 process(rst,clk) begin if(rst=0)then divcounter=0000; div_clk=0; elsif(rising_edge(clk)) then if(divcounter=1111) then divcounter=0000; div_clk=not div_clk; else divcounter=divcounter+1; end if; end if; end process;; --仿真时数码管扫描时钟，实际中需根据具体情况进行调解时钟频率 process(rst,clk) begin if(rst=0)then scancounter=00; scan_clk=0; elsif(rising_edge(clk)) then if(scancounter=11) then scancounter=00; scan_clk=not scan_clk; else scancounter=scancounter+1; end if; end if; end process;;--时钟计数部分主进程 --时钟复位 clock:process(div_clk,rst) begin if(rst=0)then sec_counter1=X0; sec_counter2=X0; min_counter1=X0; min_counter2=X0; hour_counter1=X0; hour_counter2=X0; ; --手动调分，递增 elsif(rising_edge(div_clk))then if(inc_min=0) then if(min_counter1=X9) then min_counter1=X0; if(min_counter2=X5) then min_counter2=X0; else