eda作业部分答案.docxVIP

24用VHDL设计一个实现三输入端的多数表决器。 library ieee; use ieee.std_logic_1164.all; entity bjq3 is port(a,b,c:in std_logic; y:out std_logic); end; architecture x of bjq3 is signal ty:std_logic_vector(2 downto 0); begin ty=abc; with ty select y=0 when 000, 0 when 001, 0 when 010, 1 when 011, 0 when 100, 1 when 101, 1 when 110, 1 when 111, X when others; end; 26用并行信号赋值语句设计8选1数据选择器。 library ieee; use ieee.std_logic_1164.all; entity xzq8 is port(x:in std_logic_vector(7 downto 0); sel:in std_logic_vector(2 downto 0); f:out std_logic); end; architecture a of xzq8 is begin f=x(0) when sel=000 else x(1) when sel=001 else x(2) when sel=010 else x(3) when sel=011 else x(4) when sel=100 else x(5) when sel=101 else x(6) when sel=110 else x(7) when sel=111 else X; end; 13分别用IF语句和CASE语句设计3-8译码器。 1）IF语句2）CASE语句library ieee; use ieee.std_logic_1164.all; entity de38 is port(x:in std_logic_vector(2 downto 0); y:out std_logic_vector(7 downto 0)); end; architecture a of de38 is begin process(x) begin if x=000 then y elsif x=001 then y elsif x=010 then y elsif x=011 then y elsif x=100 then y elsif x=101 then y elsif x=110 then y elsif x=111 then y else y=XXXXXXXX; end if; end process; end;library ieee; use ieee.std_logic_1164.all; entity de38_2 is port(x:in std_logic_vector(2 downto 0); y:out std_logic_vector(7 downto 0)); end; architecture a of de38_2 is begin process(x) begin case x is when 000=y when 001=y when 010=y when 011=y when 100=y when 101=y when 110=y when 111=y when others=y=XXXXXXXX; end case; end process; end; 31 原程序转换如下:? ?????ARCHITECTURE?one?OF?mux?IS???? ?????