硬件描述语言第10讲.pptVIP

硬件描述语言及器件 ;教学安排;第10讲：VHDL综合举例;1 上节内容回顾 ;计数型结构;特点 ;递变型对比;结论;枚举类型定义状态机 ;带复位的状态机;;;;2 使用完整框架编写一个4路二输入异或门;3 使用组件语句编写一个4位的移位寄存器;4 具有通道选择的单输入8输出的通道选择器;5 使用选择语句设计带使能的2－4译码器;6 使用条件语句设计74ls688比较器;7 生成ADS8402的控制时序，实现数据采集;;采集时序;设计思路;PROCESS (rst，clk) BEGIN IF(rst=‘1’) THEN Count_B=“00000”; q = ‘0’; ELSIF (clkEVENT AND clk　= ‘1’ ) THEN IF (Count_B = “10011”) THEN Count_B=“00000”; else Count_B=count_B + 1; IF (Count_B = “00000”) THEN CONVST = ‘0’; ELSIF (Count_B = “01000”) THEN RD = ‘0’; CONVST = ‘1’; ELSIF (Count_B = “01001”) THEN dat = DB; ELSIF (Count_B = “10000”) THEN RD = ‘1’; END IF; END IF; END IF; END PROCESS;; CS = ‘0’; BYTESEL = ‘0’; RESET = ‘1’; PROCESS (rst，clk) BEGIN IF(rst=‘1’) THEN Count_B=“00000”; q = ‘0’; ELSIF (clkEVENT AND clk　= ‘1’ ) THEN .. .. .. .. .. END IF; END PROCESS;;8 按定义实现写时序;ARCHITECTURE arc OF ss IS type states is (st0,st1,st2,st3); signal outc: states; Signal dat: std_logic_vector(7 downto 0); BEGIN PROCESS(clk) BEGIN IF reset=1 then outc =st0 ; dat = ; elsif clkevent and clk=1 then CASE outc IS WHEN st0 = if WREN=‘0’ then dbus = dat; WR = ‘0’; outc = st1; else outc = st0; ; CASE outc IS WHEN st0 = if WREN=‘0’ then dbus = dat; WR = ‘0’; outc = st1; else outc = st0; WHEN st1 = if ROK=‘0’ then WR = ‘1’; outc = st2; else outc = st1; WHEN st2 = dat = dat + 1; outc = st0; WHEN OTHERS = outc =st0; END CASE; end if; END PROCESS; END arc;