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CMOS Low Noise Amplifier Design Optimization Approaches Final Project Report EE201C: Modeling of VLSI Circuits and Systems (Spring 2009) By Viswakiran Popuri, M.S (EE) Electrical Engineering Dept, Univ of California Los Angeles Table of Contents Introduction……………………………………………………………..3 CMOS Low Noise Amplifier Basics……………………………………4 CMOS LNA Design from a CAD Perspective………………………….7 Approach I…………………………………………………………..8 Approach II…………………………………………………………11 Approach III………………………………………………………...14 Approach IV………………………………………………………...18 Comparison of the Optimization Approaches…………………………...22 Conclusions………………………………………………………………23 Appendix…………………………………………………………………………24 I. Introduction. In current mixed-mode integrated circuits, the analog circuits and Radio Frequency (RF) circuits represent only a small part of the total area. However, their design is very complex: a wide range of specifications have to be met and sensitivity to process variations is very high. Unlike the sophisticated synthesis Computed Aided Design (CAD )tools available for digital circuits, analog synthesis CAD tools are practically non existent and the vast majority of analog circuits are still designed manually by experts. Thus, the development time for analog blocks is far out of proportion to the die area that they consume. System-On-chips (SoCs) are becoming more and more digital. CAD has made Digital design (RTL to Layout) almost a push button job thus reducing its design time. Currently, SoCs are designed using Digital top flow leveraging on the CAD developed for Digital design. Analog/RF Design (circuit layout) time on the other hand increased in spite of fast SPICE-like simulators as more issues like a) Simulator related for e.g. DC convergence problems due to very complex models of the components. b) Process related. For e.g. Statistical (Worst case corner extraction / Monte Carlo runs) simulations are a must due to increased process va