EECS150-ComponentsandDesignTechniquesforDigital采用150元件和数字设计技术.pptVIP

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EECS150-ComponentsandDesignTechniquesforDigital采用150元件和数字设计技术.ppt

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EECS150-ComponentsandDesignTechniquesforDigital采用150元件和数字设计技术

EECS 150 - Components and Design Techniques for Digital Systems Lec 16 – Storage: DRAM, SDRAM David Culler Electrical Engineering and Computer Sciences University of California, Berkeley /~culler /~cs150 Recall: Basic Memory Subsystem Block Diagram Problems with SRAM Six transistors use up lots of area Consider a “Zero” is stored in the cell: Transistor N1 will try to pull “bit” to 0 Transistor P2 will try to pull “bit bar” to 1 If Bit lines are pre-charged high: are P1 and P2 really necessary? Read starts by precharging bit and ~bit Selected cell pulls one of them low Sense the difference 1-Transistor Memory Cell (DRAM) Write: 1. Drive bit line 2. Select row Read: 1. Precharge bit line to Vdd/2 2. Select row 3. Cell and bit line share charges Minute voltage changes on the bit line 4. Sense (fancy sense amp) Can detect changes of ~1 million electrons 5. Write: restore the value Refresh 1. Just do a dummy read to every cell. Classical DRAM Organization (Square) Row and Column Address together select 1 bit a time DRAM Logical Organization (4 Mbit) Square root of bits per RAS/CAS Row selects 1 row of 2048 bits from 2048 rows Col selects 1 bit out of 2048 bits in such a row Logic Diagram of a Typical DRAM Control Signals (RAS_L, CAS_L, WE_L, OE_L) are all active low Din and Dout are combined (D): WE_L is asserted (Low), OE_L is disasserted (High) D serves as the data input pin WE_L is disasserted (High), OE_L is asserted (Low) D is the data output pin Row and column addresses share the same pins (A) RAS_L goes low: Pins A are latched in as row address CAS_L goes low: Pins A are latched in as column address RAS/CAS edge-sensitive Basic DRAM read write Strobe address in two steps DRAM READ Timing Every DRAM access begins at: Assertion of the RAS_L 2 ways to read: early or late v. CAS Early Read Sequencing Assert Row Address Assert RAS_L Commence read cycle Meet Row Addr setup time before RAS/hold time after RAS Assert OE_L Assert Col Address Assert CAS_L Meet C