王春来毕业论文1.docVIP

独创性（或创新性）声明 本人声明所呈交的论文是我个人在导师指导下进行的研究工作及取得的研究成果。尽我所知，除了文中特别加以标注和致谢中所罗列的内容以外，论文中不包括其他人已经发表或撰写过的研究成果；也不包含为获得西安电子科技大学或其它教育机构的学位或证书而使用过的材料。与我一同工作的同志对本研究所做的任何贡献均已在论文中做了明确的说明并表示了谢意。 申请学位论文与资料若有不实之处，本人承担一切相关责任。 本人签名： 日期： 关于论文使用授权的说明 本人完全了解西安电子科技大学有关保留和使用学位论文的规定，即：研究生在校攻读学位期间论文工作的知识产权单位属西安电子科技大学。本人保证毕业离校后，发表论文或使用论文工作成果时署名单位仍然为西安电子科技大学。学校有权保留送交论文的复印件，允许查阅和借阅论文；学校可以公布论文的全部或部分内容，可以允许采用影印、缩印或其它复制手段保存论文。鉴于本论文的研究成果是同中外合资西安XX公司（Xi’an XX Microelectronics Inc.）签订过保密合同，所以本论文的保密期限为论文提交后的五年内有效。 本人签名： 日期： 导师签名： 日期： 摘要 以外商委托的科研项目“深亚微米电源管理类集成电路及各种数模混合集成电路的关键技术理论研究与设计”为背景，作者承担了高效电流模 Buck型DC/DC 斜率补偿 稳定性 可测性 ABSTRACT A high efficiency current mode synchronous buck regulator IC is designed on the basis of the project “Theoretical research and design of key techniques for deep-submicron power management IC and mixed IC”. The whole simulation has been completed by using the EDA softwares, such as Cadence, Hspice, and the layout design is also finished. At present, the chip is being taped out in Hynix. Beginning from the switching mode regulator, a high efficiency current mode synchronous buck DC/DC is designed after an in-depth systemic study on the current-mode switching regulator. By adopting the technologies of synchronous rectification, double operation mode and low dropout operation, the efficiency of this design is up to 96%. In order to prevent the sub-harmonic oscillation at high duty cycles, slope compensation is used. What is special is that the design provides a clamp circuit that can adjust its thresholds with respect to the magnitude of the slope compensation signal so that a substantially constant maximum current limit of the regulator may be remained at greater duty cycles. A macro model is also created to obtain the bode plots for appropriate frequency compensation. Finally, the circuits for testability are designed to shorten the test time and get more