数电课件ch_07_st.pptVIP

? 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed ? 2009 Pearson Education, Upper Saddle River, NJ 07458. All Rights Reserved Floyd, Digital Fundamentals, 10th ed Digital Fundamentals Tenth Edition Floyd Chapter 7 ? 2008 Pearson Education Combinational circuit vs Sequential circuit 組合電路(Combinational circuit)並不會儲存之前發生過的狀態 循序電路(Sequential circuit)會根據目前的狀態來決定下一次的輸出狀態 A latch is a temporary storage device that has two stable states (bistable). It is a basic form of memory. Summary Latches The S-R (Set-Reset) latch is the most basic type. It can be constructed from NOR gates or NAND gates. With NOR gates, the latch responds to active-HIGH inputs; with NAND gates, it responds to active-LOW inputs. NOR Active-HIGH Latch NAND Active-LOW Latch R S Q Q Q S R Q The active-HIGH S-R latch is in a stable (latched) condition when both inputs are LOW. Summary Latches R S Q Q Assume the latch is initially RESET (Q = 0) and the inputs are at their inactive level (0). To SET the latch (Q = 1), a momentary HIGH signal is applied to the S input while the R remains LOW. 0 1 0 R S Q Q 1 0 0 To RESET the latch (Q = 0), a momentary HIGH signal is applied to the R input while the S remains LOW. 0 0 1 0 1 0 Latch initially RESET Latch initially SET S R The active-LOW S-R latch is in a stable (latched) condition when both inputs are HIGH. Summary Latches Q Q 1 1 0 1 0 1 Latch initially RESET Q Q 1 1 0 1 0 1 Latch initially SET S R Assume the latch is initially RESET (Q = 0) and the inputs are at their inactive level (1). To SET the latch (Q = 1), a momentary LOW signal is applied to the S input while the R remains HIGH. To RESET the latch a momentary LOW is applied to the R input while S is HIGH. Never apply an active set and reset at the same time (invalid). The active-LOW S-R latch is available as the 74LS279A IC. Summary Latches 1Q 2Q 3Q 4Q 74LS279A It features four internal latches with two having two