Interfacing Two Clock Domains(双时钟域接口).pdf

Interfacing Two Clock Domains There are times when a designer needs to interface two systems working at two different clocks. This interfacing is difficult in the sense that design becomes asynchronous at the boundary of interface, which results in setup and hold violation, metastability and unreliable data transfers. So we need to go out for special design and interfacing techniques. Any two systems are considered asynchronous to each other: When they operate at two different frequency When they operate at same frequency, but at two different clock phase angles Here we have two systems, which are asynchronous in nature to each other. In such a case if we need to do data transfer, there are very few methods to achieve this:  Handshake Signaling method.  Asynchronous FIFO. Handshake Signaling In this method the system (module) A sends data to system/module B based on the handshake signals ack and req signals. The protocol for this uses the same old method that is found with 8155 chip used with 8085. Protocol  Transmitter asserts the req (request) signal, asking the receiver to accept the data on the data bus.  Receiver asserts the ack (acknowledge) signal, asserting that it has accepted the data. This method is straightforward, but it too has got loop holes: when system B samples the systems As req line and System A samples system Bs ack line, they are done with respect to their internal clock, so there will be setup and hold time violation. To avoid this we go for double or triple stage synchronizers, which increase the MTBF and thus are immune to metastability to a good extent. The figure below shows how this is done with respect to the above example. If we do the double or triple stage synchronizing, then the transfer rate comes down, due to the fact that a