有限状态机verilog描述方法.pdfVIP

关于下图的设计 方法一： module fsm (Clock, Reset, A, F, G); input Clock, Reset, A; output F,G; reg [1:0] state, Nextstate; parameter Idle = 2’b00, Start = 2’b01, Stop = 2’b10, Clear = 2’b11; always @(posedge Clock) if (!Reset) begin state = Idle; end else state = Nextstate; always @( state or A ) begin F=0; G=0; if (state == Idle) begin if (A) Nextstate = Start; else