西电verilog课件第七章课件.ppt

* * Microelectronics School Xidian University module t_trigger(clk,rst,T,dout); input clk,rst,T; output dout; reg dout; always @(posedge clk or posedgerst) if(rst==1) dout=1b0; else if(T==1) dout=~dout; endmodule module t_trigger_tb; reg clk,rst,T; wire dout; always begin #10 clk=1b1; #10 clk=1b0; end initial begin clk=1b0; rst=1b0;T=1b0; #10 rst=1b1;T=1b1; #10 rst=1b0;T=1b0; #20 T=1b1; #20 T=1b0; #20 T=1b1; end t_trigger u1(clk,rst,T,dout); endmodule 7.4 计数器 * * Microelectronics School Xidian University 7.4.1 任意模值计数器 1. 反馈清零计数器 图7.4