LDO噪声详解教案.pdfVIP

Power Management Texas Instruments Incorporated LDO 噪声详解 LDO noise examined in detail 作者：Masashi Nogawa ， By Masashi Nogawa 德州仪器(TI) 线性稳压器高级系统工程师 Senior Systems Engineer, Linear Regulators 引言 Introduction Requirements and expectations for telecommuni- 图 负反馈环路 随着通信信道的复杂度和可靠性不断增加，人们 Figure 1. Negative-feedback loop of LDO 1 LDO cation systems continue to evolve as complexity 对于电信系统的要求和期望也不断提高。这些通 and reliability of the communication channels continue to increase. These communication sys- V 信系统高度依赖于高性能、高时钟频率和数据转 IN tems rely heavily on high-performance, high-speed 换器器件，而这些器件的性能又非常依赖于系统 clocking and data-converter devices. The perform- 电源轨的质量。当使用一个高噪声电源供电时， ance of these devices is highly dependent on the + NFET 时钟或者转换器 无法达到最高性能。仅仅只 Error IC quality of system power rails. A clock or converter Amp VGATE 是少量的电源噪声，便会对性能产生极大的负面 – IC simply cannot achieve top performance when + powered by a dirty power supply. Just a small 影响。本文将对一种基本 LDO 拓扑进行仔细研 VREF OUT Node (VOUT) amount of noise on the power supply can cause – 究，找出其主要噪声源，并给出最小化其输出噪 dramatic negative effects on the performance. 声的一些方法。 COUT This article examines a basic LDO topology to find R1 its dominant noise sources and suggests ways to 表明电源品