Praet, “A graph based processor model for retargetable code generation.pdf

A Graph Based Processor Model for Retargetable Code Generation J. Van Praet D. Lanneer G. Goossens W. Geurts H. De Man IMEC, kapeldreef 75, 3001 Leuven, Belgium e-mail : vanpraet@imec.be Abstract model, called instruction set graph (ISG). All tools are pro- cessor independent and are retargetable by only providing Embedded processors in electronic systems typically are a new or modified ISG processor model. tuned to a few applications. Development of processor spe- This paper describes the ISG processor model and its cific compilers is prohibitively expensive and as a result use. Section 2 explains the requirements for an ASIP pro- such compilers, if existing, yield code of an unacceptable cessor model in further detail and compares with related quality. To improve this code quality, we developed a re- work. Section 3 provides the basics of the ISG model. Sec- targetable and optimising code generator. It uses a graph tion 4 shows how the code generation tasks can be defined based processor model that captures the connectivity, the formally in terms of the ISG model. Finally, Section 5 and par