考虑量子效应的纳米MOS器件阈值电压及栅电容的建模与模拟.pdfVIP

Abstract Abstract As we all know, the key to achieve development of the information society is all kinds of computers and communications machines which are all based on micro- electronic products. At present，The core of Microelectronics industry is MOS IC. Since the 1960s, IC development has been follow the law what the Intels co-founder Gordon E. Moore predicted. IC integration every three years growth of 4 times, feature size was reduced 2 three times each. 40 years, In order to improve the performance of the electronic system integration, lower costs, and the device feature size is shrinking, the processing accuracy of production is improving, the area of silicon is growing, IC cost performance also improved rapidly. MOS device that used in Modern electronics is actually based on CMOS (complementary metal oxide semiconductor) process, Because of low power consumption and high integration, the technology has become the mainstream. The feature size of IC chips also from 1978 to 10 um access to the nanoscale. As predicted, in the first half of the 21st century, the process technology with the scaling of the silicon-based CMOS dimensions will be the mainstream in the microelectronics industry. With the continuous improvement of integration, the device feature size decreases, The Study of the technical challenges and physical problems has become an urgent and important issue. The Study of the technical challenges and physical problems has become an urgent and important issue. In order to understand the process of narrowing devices limit, we should model and simulate the nano-device, re-evaluate the performance of devices. And nano-device