DDR3设计调试教案.doc

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2017-06-11 发布于湖北
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DDR3设计调试教案.doc

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DDR3设计配置：关于配置寄存器：部分配置寄存器基地址在 0x2100_0000 #define DDR3_BASE_ADDR (0 #define DDR_SDCFG (*(unsigned int*)(DDR3_BASE_ADDR + 0) #define DDR_SDRFC (*(unsigned int*)(DDR3_BASE_ADDR + 0) #define DDR_SDTIM1 (*(unsigned int*)(DDR3_BASE_ADDR + 0) #define DDR_SDTIM2 (*(unsigned int*)(DDR3_BASE_ADDR + 0) #define DDR_SDTIM3 (*(unsigned int*)(DDR3_BASE_ADDR + 0) #define DDR_PMCTL (*(unsigned int*)(DDR3_BASE_ADDR + 0) #define RDWR_LVL_RMP_WIN (*(unsigned int*)(DDR3_BASE_ADDR + 0x000000D4)) #define RDWR_LVL_RMP_CTRL (*(unsigned int*)(DDR3_BASE_ADDR + 0x000000D8)) #define RDWR_LVL_CTRL (*(unsigned int*)(DDR3_BASE_ADDR + 0x000000DC)) #define DDR_ZQCFG (*(unsigned int*)(DDR3_BASE_ADDR + 0x000000C8)) #define DDR_PHYCTRL (*(unsigned int*)(DDR3_BASE_ADDR + 0x000000E4)) 大部分寄存器位于chip-level registers 0x0262_0000 #define DDR3PLLCTL0 (*(unsigned int*)(0) #define DDR3PLLCTL1 (*(unsigned int*)(0) #define DATA0_WRLVL_INIT_RATIO (*(unsigned int*)(0x0262040C)) #define DATA1_WRLVL_INIT_RATIO (*(unsigned int*)(0) #define DATA2_WRLVL_INIT_RATIO (*(unsigned int*)(0) #define DATA3_WRLVL_INIT_RATIO (*(unsigned int*)(0) #define DATA4_WRLVL_INIT_RATIO (*(unsigned int*)(0x0262041C)) #define DATA5_WRLVL_INIT_RATIO (*(unsigned int*)(0) #define DATA6_WRLVL_INIT_RATIO (*(unsigned int*)(0) #define DATA7_WRLVL_INIT_RATIO (*(unsigned int*)(0) #define DATA8_WRLVL_INIT_RATIO (*(unsigned int*)(0x0262042C)) #define DATA0_GTLVL_INIT_RATIO (*(unsigned int*)(0x0262043C)) #define DATA1_GTLVL_INIT_RATIO (*(unsigned int*)(0) #define DATA2_GTLVL_INIT_RATIO (*(unsigned int*)(0) #define DATA3_GTLVL_INIT_RATIO (*(unsigned int*)(0) #define DATA4_GTLVL_INIT_RATIO (*(unsigned int*)(0x0262044C)) #define DATA5_GTLVL_INIT_RATIO (*(unsigned int*)(0) #define DATA6_GTLVL_INIT_RATIO (*(unsigned int*)(0) #define DATA7_GTLVL_INIT_RATIO (*(u