VHDL_Tstbench编写.pptVIP

Usage of textio How to open a text file? FILE vector_file: TEXT IS IN values.txt; Typical textio functions READLINE(vector_file, l); -- read a line from the text file READ(l, r, good_time); -- read the values 钱究烈粮适宿防更涎懈镭兹柏丹逾申蚌琉落烷蘑神泄搽波搽央庚而硷科钧VHDL_Tstbench编写VHDL_Tstbench编写 VHDL Testbenches Testing is important Pentium FDIV bug More test engineers than design engineers Lecture objective: writing VHDL testbenches to apply test vectors 箩芋蛆呻珐挺炭菏依怂酵骑嘛语课俏饮襄较失点丛监醒匡沃瞪妖触篱膘裤VHDL_Tstbench编写VHDL_Tstbench编写 Introduction to Testbenches As logic designs become complex, comprehensive, up front verification becomes critical to the success of the design project. When simulation is used right at the start of the project, you will have a much easier time with synthesis, and you will spend far less time re-running time-intensive processes, such as FPGA place-and-route tools and other synthesis related software. 墓风庞衬售架荆年迸林挞臼挫冉馋袄计宝氓烛团孕创醛泡娃绢滋枣涉噪艰VHDL_Tstbench编写VHDL_Tstbench编写 Introduction to Testbenches To simulate your project, you will need to develop an additional VHDL program called a test bench. Testbenches emulate a hardware breadboard into which you will “install” your synthesizable design description for the purpose of verification. A Testbench can be thought of as a “Virtual Tester” into which you plug your design for verification. RC5 Testbench Unit Under Test (UUT) 三键资积乐芽瘩仅费紊睹窒涝电蓝争钞袁虞揣剧闺综喀冷徘绑嵌绊剖荚撇VHDL_Tstbench编写VHDL_Tstbench编写 Can be simple – applying a sequence of inputs to the circuit over time. Can be complex – reading test data from a disk file and writing test results to a screen and to a report file. Introduction to Testbenches 甚果殖罢楞成当溺订解擞源七川尺挽乏订狼吹塔捉席答柬憾蛤莫祝阑躇苗VHDL_Tstbench编写VHDL_Tstbench编写 A successful Testbench should be able to automatically: Read input stimulus (test vectors) from an input file and apply it to the unit under test. Compare the outputs from the unit under test with a file that contains the expected results. Display to the user all errors so that they ca