FPGA综合设计实例.ppt

第十章综合设计实例 1 键盘扫描与显示 矩阵式键盘:行,列 数码管显示 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity key_scan is port(column:in std_logic_vector(3 downto 0); --列状态 scan_cnt:in std_logic_vector(3 downto 0);---扫描字 row:out std_logic_vector(3 downto 0);---行状态 key_pressed:out std_logic);-----按键有效与否,后续判断为零则为有键按下 end ; architecture rtl of key_scan is begin row=1110 when scan_cnt(3 downto 2)=00 else 1101 when scan_cnt(3 downto 2)=01 else 1011 when scan_cnt(3 downto 2)=10 else 0111; key_pressed=column(0) when scan_cnt(1 downto 0)=00 else column(1) when scan_cnt(1 downto 0)=01 else column(2) when scan_cnt(1 downto 0)=“10 else column(3); end rtl ; 按键处理控制模块 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity scan_count is port(clk:in std_logic;--clock scan_clk:in std_logic;--1khz clk key_pressed:in std_logic;--检测按键有效与否,停止计数. scan_cnt:out std_logic_vector(3 downto 0));--计数 end; architecture behav of scan_count is signal qscan:std_logic_vector(3 downto 0); begin scan_1:process(clk,scan_clk,key_pressed) begin if(clkevent and clk=1)then if(scan_clk=1 and key_pressed=1)then qscan=qscan+1; end if; end if; end process; scan_cnt=qscan; end; 按键消抖控制模块 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity debounce is port(key_pressed:in std_logic; clk:in std_logic;--同步时钟 scan_clk:in std_logic;--1khz clock key_valid:out std_logic); end; architecture behav of debounce is begin debounce:process(clk,scan_clk,key_pressed) variable dbnq:std_logic_vector(5 downto 0); begin if(key_pressed=1)then dbnq:=111111;--unkey_pressed,count reset at 63 elsif(clkevent and clk=1)then